Lisa Logan, applications manager for scanning acoustic microscopes, PVA TePla Analytical Systems
The concept behind advanced 3D packaging is to stack multiple dies or wafers in a vertical direction or z-dimension to achieve a smaller size and better performance at lower power and cost. However, as 3D packages become increasingly complex, so do the challenges in identifying defects in multiple layers of stacked dies, silicon interposers and interconnections such as through-silicon vias (TSVs) and fine-pitch microbumps.
Since there is less accessibility to internal components and a need to scan multiple, stacked layers, the focus is now shifting to methods of non-destructive testing both in manufacturing and for failure analysis.
3D advanced packaging
In general, the term 3D packaging applies to products manufactured by stacking silicon wafers or dies and interconnecting them vertically. This covers many integration schemes, including 3D wafer-level packages (WLPs), system in packages (SiPs), package on packages (PoPs), 2.5D and 3D packages, stacked integrated circuits (ICs) and other forms of heterogeneous integration.
Early 3D packages relied on interconnects such as wire bonding and flip chips to achieve vertical stacking. Today, communication between chips often involves a silicon or organic interposer or bridge, with TSVs. The interposer acts as the bridge between the chips and the board, while increasing the input/outputs (I/Os) and bandwidth.
Now, the concept of modular chips, or chiplets, is gaining momentum for advanced packaging. In this approach, chiplets from third-party vendors are used to build a package or system by stacking the components vertically. By selecting the optimum central processing unit (CPU), I/O, field-programmable gate array (FPGA), radio frequency (RF) or graphics processing unit (GPU), for example, the chiplets can be mixed-and-matched using a die-to-die interconnect scheme involving a silicon interposer, a silicon bridge or high-density fan-out.
Intel has embraced this approach, recently announcing its Foveros 3D packaging technology, which allows complex, heterogenous logic chips to be stacked directly on top of each other. An active interposer is used instead of a typical passive silicon interposer. As an alternative, the company is also offering its silicon bridge technology, known as Embedded Multi-die Interconnect Bridge (EMIB).
Furthermore, the Defense Advanced Research Projects Agency (DARPA), an agency of the US Department of Defense, plans to develop a large catalogue of third-party chiplets for commercial, military and aerospace applications. The goal of DARPA’s Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS) programme is to increase overall system flexibility and reduce design time by as much as 70 percent. According to Andreas Olofsson, a program manager in the Microsystems Technology Office (MTO) at DARPA, “The vision of CHIPS is an ecosystem of discrete modular, reusable IP blocks, which can be assembled into a system using existing and emerging integration technologies.”
Still, there are challenges in making the chiplet concept work, including how to verify and test the individual chiplets from a variety of third-party vendors. Integrating multiple chiplets into stacked 3D packages also requires high-density interconnections, all of which are potential sources of failure. In comparison with other 3D package types, for example, stacked dies with TSVs, they require much smaller, finer pitch solder bumps that create additional challenges in defect detection.
A single defective chiplet or poor interconnection can render the entire 3D package non-functional. This is driving the requirement for 100 percent inspection during manufacturing, ideally using non-destructive testing methods.
Non-destructive testing of 3D Packages
The challenge today is to perform 100 percent inspection at relatively high throughput to identify and remove 3D packages or components that do not meet quality requirements. Among the available non-destructive methods, scanning acoustic microscopy (SAM) is the most widely used for testing and failure analysis involving stacked dies or wafers.
SAM utilises ultrasound waves to non-destructively examine internal structures, interfaces and surfaces of opaque substrates. The resulting acoustic signatures can be constructed into 3D images that are analysed to detect and characterise device flaws such as cracks, delamination, inclusions and voids in bonding interfaces, as well as to evaluate soldering and other interface connections.
The unique characteristic of acoustic microscopy is its ability to image the interaction of acoustic waves with the elastic properties of a specimen. In this way, the acoustic microscope is used to image the interior of an opaque material.
SAM works by directing focused sound from a transducer at a small point on a target object. The sound, on hitting a defect, inhomogeneity or boundary inside material, is partly scattered and will be detected. The transducer transforms the reflected sound pulses into electromagnetic pulses that are displayed as pixels with defined greyscale values, thereby creating an image.
To produce an image, samples are scanned point by point and line by line. Scanning modes range from single-layer views to tray scans and cross-sections. Multi-layer scans can include up to 50 independent layers. Images from different depths can be combined into a single scan as well, a process called tomographic acoustic micro imaging.
If higher throughput is required, up to four transducers can scan simultaneously. Multiple transducers can be used on a single substrate and the images then stitched together, or multiple transducers can scan multiple substrates simultaneously.
SAM provides non-destructive imaging of defects and delaminations in die and package materials. It is particularly useful for the inspection of small, complex 3D devices, being highly sensitive to the presence of delaminations and air-gaps at sub-micron thicknesses.
The most common defects in 3D packaging are: delamination, cracks in the substrate; die tilt; misalignment and voids in the microbumps; bump defects; solder bridging; popcorn cracks; voids in the underfill; and voids and delamination in the TSVs.
The resolution of the microscopic image depends on the acoustic frequency, the material properties and aperture of the transducer. The frequency of the ultrasonic signals generated for 3D package inspection is typically within 15 to 300 MHz.
Transducers, play a critical role in scanning acoustic microscopes, so much so that scanning acoustic microscope manufacturers such as PVA TePla Analytical Systems (PVA TePla) choose to design and manufacture them themselves.
The frequency of transducers’ ultrasonic signals can be increased into the GHz range, making it possible to detect defects in the sub-micron range. For example, one of PVA TePla’s high-resolution, GHz frequency scanning acoustic microscopes is capable of detecting voids in TSVs of 5 μm diameter and 50 μm depth, immediately after plating.
Three-dimensional chip manufacturers are trying to push the limits of what they can detect in terms of defects. Therefore, the selection of a scanning acoustic microscope often comes down to the highest resolution and throughput speeds at which 100 percent inspection can be achieved.
PVA TePla Analytical Systems
Reference
1Olofsson, A. Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) [programme information]. Defense Advanced Research Projects Agency (DARPA). Available at: bit.ly/2JpVgBC
